Cadence Design Systems, Inc. announced today multi-protocol Serializer/Deserializer (SerDes) PHY IP for PCI Express 2.0 and PCIe 3.0 technology for TSMC's 16nm FinFET Plus (16FF+) process have passed PCI-SIG compliance testing.
"PCIe 3.0 and PCIe 2.0 compliance was achieved with first 16FF+ silicon. The early availability of these products enables our customers to tapeout their leading-edge mobile, storage and enterprise designs sooner and with reduced risk," said Osman Javed, product marketing director at Cadence. "These flexible multi-protocol solutions provide customers a unique combination of SoC differentiation and future proofing.
The complete solution achieved compliance 12 months after the announcement of the 16FF+ process, furthering designer’s confidence the Cadence IP will operate to the specification they need.
